Название: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Hardware Architectures Автор: Sudeep Pasricha, Muhammad Shafique Издательство: Springer Год: 2024 Страниц: 418 Язык: английский Формат: pdf (true) Размер: 21.8 MB
This book presents recent advances towards the goal of enabling efficient implementation of Machine Learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying Machine Learning to innovative application domains, exploring the efficient hardware design of efficient Machine Learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits.
Machine Learning (ML) has emerged as a prominent approach for achieving state-of-the-art accuracy for many data analytic applications, ranging from computer vision (e.g., classification, segmentation, and object detection in images and video), speech recognition, language translation, healthcare diagnostics, robotics, and autonomous vehicles to business and financial analysis. The driving force of the ML success is the advent of neural network (NN) algorithms, such as deep neural networks (DNNs)/Deep Learning (DL) and spiking neural networks (SNNs) with support from today’s evolving computing landscape to better exploit data and thread-level parallelism with ML accelerators.
Current trends show an immense interest in attaining the powerful abilities of NN algorithms for solving ML tasks using embedded systems with limited compute and memory resources, i.e., so-called Embedded ML. One of the main reasons is that embedded ML systems may enable a wide range of applications, especially the ones with tight memory and power/energy constraints, such as mobile systems, Internet of Things (IoT), edge computing, and cyber-physical applications. Furthermore, embedded ML systems can also improve the quality of service (e.g., personalized systems) and privacy as compared to centralized ML systems (e.g., based on cloud computing). However, state-of-the-art NN-based ML algorithms are costly in terms of memory sizes and power/energy consumption, thereby making it difficult to enable embedded ML systems. This book explores and identifies the most challenging issues that hinder the implementation of embedded ML systems.
This volume of the book focuses on addressing these challenges from a hardware perspective, with multiple solutions towards the design of efficient accelerators, memory, and emerging technology substrates for embedded ML systems.
Contents:
Part I. Efficient Hardware Acceleration for Embedded Machine Learning Massively Parallel Neural Processing Array (MPNA): A CNN Accelerator for Embedded Systems Photonic NoCs for Energy-Efficient Data-Centric Computing Low- and Mixed-Precision Inference Accelerators Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations Efficient Hardware Acceleration of Emerging Neural Networks for Embedded Machine Learning: An Industry Perspective Part II. Memory Design and Optimization for Embedded Machine Learning An Off-Chip Memory Access Optimization for Embedded Deep Learning Systems In-Memory Computing for AI Accelerators: Challenges and Solutions Efficient Deep Learning Using Non-volatile Memory Technology in GPU Architectures SoC-GANs: Energy-Efficient Memory Management for System-on-Chip Generative Adversarial Networks Using Approximate DRAM for Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Part III. Efficient Software Design for Embedded Machine Learning On-Chip DNN Training for Direct Feedback Alignment in FeFET Platform-Based Design of Embedded Neuromorphic Systems Light Speed Machine Learning Inference on the Edge Low-Latency, Energy-Efficient In-DRAM CNN Acceleration with Bit-Parallel Unary Computing
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