 Название: Versatile Hardware Analysis Techniques: From Waveform-based Analysis to Formal Verification
Автор: Lucas Klemmer, Daniel Große
Издательство: Springer
Год: 2025
Страниц: 199
Язык: английский
Формат: pdf (true), epub
Размер: 19.4 MB
This book describes several versatile hardware analysis techniques that tackle existing and new challenges. These techniques cover different phases of the hardware development process, including the verification, debugging, and post-synthesis optimization phases. The authors introduce the Waveform Analysis Language (WAL), which allows users to code analysis tasks in the form of programs that run on waveforms. The book covers processor verification, formal microcode verification, programmable automated waveform analysis demonstrated for a large variety of previously manual analysis tasks, as well as netlist optimization leveraging formal methods. All methods are available as open source, typically include examples on RISC-V analysis problems, providing a strong foundation for the community.
Introduces automated waveform analysis based on a DSL to execute programs on waveforms
Includes practical examples for waveform analysis including demonstrations for RISC-V processors
Presents novel approaches for processor verification, microcode verification & netlist optimization with formal methods
With the slowing down of Moore’s law, the times of ever-increasing processor performance gains through optimizations in the manufacturing process come to an end. However, expectations for improved performance and efficiency have not slowed down. Instead, developments such as Apples M1 processor or the unprecedented need for powerful processing units for Artificial Intelligence (AI) tasks nourish the expectations from customers and businesses for ever-increasing performance.
In an attempt to keep up with these rising expectations, large parts of the industry are pivoting toward highly application-specific designs. These highly domain-specific designs are built for a single application only or for a small group of similar applications. One prominent example of this is the intense competition for AI accelerators. Today, commercial accelerators are available from many companies in the digital design and EDA space. The same development can be observed in academia too, where recently, AI-related research became one of the hot topics. Another prime example is the emergence and fast adoption of the modular and open-standard RISC-V ISA. By separating most parts of the ISA into optional extensions, RISC-V scales from the tiniest embedded systems up to the largest High Performance Computing (HPC) applications. Further, RISC-V not only allows fine-grained control over which extension is used, but it also allows users to define their own custom instructions. The customizability and the openness of RISC-V have led to the availability of a wide range of Intellectual Property (IP) and increased industry adoption.
Of course, a drive to more application-specific designs has meant no slowdown in the ever-increasing size and complexity of designs. Taken together, this means that hardware development is not only getting more complicated due to increasing complexity but also due to a significantly increasing number of designs. From the design perspective, much work has been done recently to accommodate these challenges. This includes work on modern code-generator-based Hardware Description Languages (HDLs) that allows extensive parameterization to enable quickly adapting to varying needs or the continued work on Virtual Prototypes (VPs) that help in design space exploration and allow earlier software development.
During development of a new hardware design, multiple phases are passed. At a very high level, the hardware development process can be broken down into seven phases: specification, design, verification, debug, synthesis, post synthesis optimization, and fabrication. After the specification is ready, the design space of possible implementations is typically explored using high-level models such as VPs at the Electronic System Level (ESL) leveraging Transaction Level Modeling (TLM). If the high-level architecture is decided upon, it is commonly refined to the hardware level using an Register Transfer Level (RTL) description.
Contents:
1. Introduction
2. Background
3. Processor Verification by Equivalent Program Execution
4. A Formally Verified Microcoded RISC-V Platform
5. The Waveform Analysis Language
6. Programmable Analysis of RISC-V Processors Using WAL
7. HDL-Integrated Waveform Analysis
8. An Interactive Debugging Methodology Based on WAL
9. Netlist Optimization Using Formal Methods Under External Constraints
10. Conclusion and Outlook
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Versatile Hardware Analysis Techniques: From Waveform-based Analysis to Formal Verification 
